7 Segment Displays

By xantus on Friday 5 March 2010 04:25
Category: Verilog examples, Views: 8.593

An easy way to add debug capabilities to your project is by using the 7-segment displays. The following piece of verilog code shows you how to control the 4 multiplexed common-cathode displays. The digitx inputs are BCD. The fifth bit (digitx[4]) is for blanking the digit (1=off, 0=on).

7-segment displays
Verilog code

C: Seven_segment_displays
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module seven_segment_displays(digit1, digit2, digit3, digit4, clk, A, B, C, D, E, F, G, DP, SEG_A, SEG_B, SEG_C, SEG_D);
// Port declarations
  input [4:0] digit1;  //Least significant digit input
  input [4:0] digit2;
  input [4:0] digit3;
  input [4:0] digit4;  // Most significant digit input
  input clk;
 
  output reg A;
  output reg B;
  output reg C;
  output reg D;
  output reg E;
  output reg F;
  output reg G;
  output reg DP;
  output reg SEG_A;
  output reg SEG_B;
  output reg SEG_C;
  output reg SEG_D;
 
// Internal Variables
  reg [4:0] display;
 
initial SEG_D = 1;
 
// Multiplex digits
  always @ (posedge clk) 
   begin
    {SEG_A, SEG_B, SEG_C, SEG_D} <= {SEG_B, SEG_C, SEG_D, SEG_A};
 
    case({SEG_A, SEG_B, SEG_C, SEG_D})
      4'b0001: display <= digit1;
      4'b0010: display <= digit2;
      4'b0100: display <= digit3;
      4'b1000: display <= digit4;
    endcase
   end
 
// Convert BCD to output
  always @ (posedge clk)
   begin
    if(display[4]) {G, F, E, D, C, B, A, DP} <= 8'b00000000;
    else
      case(display)
        5'h01: {G, F, E, D, C, B, A, DP} <= 8'b00001100;    //      --A--- 
        5'h02: {G, F, E, D, C, B, A, DP} <= 8'b10110110;    //     /     /
        5'h03: {G, F, E, D, C, B, A, DP} <= 8'b10011110;    //     F     B
        5'h04: {G, F, E, D, C, B, A, DP} <= 8'b11001100;    //    /     /
        5'h05: {G, F, E, D, C, B, A, DP} <= 8'b11011010;    //    --G--- 
        5'h06: {G, F, E, D, C, B, A, DP} <= 8'b11111010;    //   /     /
        5'h07: {G, F, E, D, C, B, A, DP} <= 8'b00001110;    //   E     C
        5'h08: {G, F, E, D, C, B, A, DP} <= 8'b11111110;    //  /     /
        5'h09: {G, F, E, D, C, B, A, DP} <= 8'b11011110;    //  --D---   DP
     // 5'h0A: {G, F, E, D, C, B, A, DP} <= 8'b11101110;
     // 5'h0B: {G, F, E, D, C, B, A, DP} <= 8'b11111000;
     // 5'h0C: {G, F, E, D, C, B, A, DP} <= 8'b01110010;
     // 5'h0D: {G, F, E, D, C, B, A, DP} <= 8'b10111100;
     // 5'h0E: {G, F, E, D, C, B, A, DP} <= 8'b11110010;
     // 5'h0F: {G, F, E, D, C, B, A, DP} <= 8'b11100010;
        5'h00: {G, F, E, D, C, B, A, DP} <= 8'b01111110;
      endcase
   end
 
   end
 
endmodule

Conclusion
The clock used for multiplexing should be at least 250Hz. The clock should be no faster than 5 kHz to avoid ghosting.
When synthesized, the code will use between 20 (with no blanking) and 34 (with blanking and 0-F digits) LEs.
http://www.greenbird.info/img.php?h&b=7-segment-displays&f

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