PS/2 Keyboard Communication

By xantus on donderdag 18 februari 2010 13:41 - Comments (1)
Category: Verilog examples, Views: 16.503

PS/2 keyboard communication is actually a very simply protocol too implement on a FPGA. The clock is provided by the keyboard and the data is sent in 11-bit frames. The frame-bits are:

1 start bit; always 0
8 data bits (LSB first)
1 parity bit (odd parity)
1 stop bit; always 1

The following waveform¹⁾ gives a graphical representation of de data stream:
PS/2 waveform

As shown, the keyboard will place the data on the data line on de positive edge. Data may be read on the negative edge of the clock.

PS/2 logic

C: PS/2

module ps(clk,data,scan_code,parity_error,rdy);
// Port declarations
 input clk;              // PS_2 clock input
 input data;             // PS_2 data input
 output[7:0] scan_code;  // Scan_code output
 output parity_error;    // Parity output
 output rdy;             // Data ready output
 
// Internal Variables 
 reg[9:0] register;
 reg[3:0] counter;
 reg parity_error, rdy;
 
 assign scan_code = register[9:2];
 assign parity = register[1];
 
// PS/2 logic
 always @ (negedge clk)
  begin
   register <= {register[8:0], data}; // receive data
   if (counter == 4'b1011)
     counter <= 4'b0000;
   else
     counter <= counter + 4'b1;
  end
 
// PS/2 parity logic
 always @ (posedge clk)
  begin
   if (counter == 4'b1011)
     if (!parity == ^scan_code) // parity check (odd parity)
      rdy <= 1'b1;
     else
      parity_error <= 1'b1;
   else  // not all 10 bits receiverd yet
    begin
     rdy <= 1'b0;
     parity_error <= 1'b0;
    end
  end
 
endmodule

Conclusion

As the decoder is basically only a serial to parallel shift registry with some XOR's for the parity. Compilation will show that it only requires 17 LE's.
The downside to the whole PS/2 keyboard thing is that it requires a 256 byte ROM to convert (most) scan codes to the corresponding ASCII value.

¹⁾ Image © www.computer-engineering.org

http://www.greenbird.info/img.php?h&b=ps2&f

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Comments

By Akshay, donderdag 18 april 2013 19:32

what will the output be for the program. also can you give a pin assignment UCF file for this just so we know more clearly what to expect off this program.. when we run it on an FPGA board..

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