SRAM controller

By xantus on Monday 8 February 2010 11:53
Category: Verilog examples, Views: 6.893

Sram exampleA problem with many SRAM ic's is that they are asynchronous. This is tricky too use in the synchronous FPGA world. This example shows how to interface with a cheap (4.271)) and high speed (80 MHz) CY7C1041CV33, a 4Mbit (256k x16) SRAM ic, with a MAXII CPLD.

Controller Logic


C: SRAM controller
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module sram_ctrl(clk, wren, d, q, address, BHE, BLE, WE, CE, OE, IO, A);
input clk;
input wren;
input [15:0] d;
input [17:0] address;
output reg [15:0] q;
 
output reg BHE; //byte write select input IO[15:0] (active low)
output reg BLE; //byte write select input IO[7:0] (active low)
output reg WE;  //write enable (active low)
output reg CE;  //chip enable (active low)
output reg OE;  // output enable (active low)
inout [15:0] IO; // data
output reg [17:0] A; // address
 
reg io_oe;
reg [15:0] buffer_d;
 
assign IO = io_oe ? buffer_d : 15'bZ;
 
always @ (posedge clk)
 begin
  if (wren)
   begin // write data
    A <= address;
    OE <= 1;
    CE <= 0;
    WE <= 0;
    BHE <= 0;
    BLE <= 0;  
    io_oe <= 1;
   end 
  else
   begin // read data
    A <= address;
    CE <= 0;
    OE <= 0;
    BHE <= 0;
    BLE <= 0;
    WE <= 1;
    io_oe <= 0;
   end
   buffer_d <= d;
 end
 
always @ (negedge clk)
  if (wren==0)
   begin // read data
     q <= IO;
   end
 
endmodule

Result

And the result….

Simulation SRAM

The simulation shows 7 read and 2 write operations. The IO bus is the input on the bidirectional bus and the IO~result is the output on the bidirectional pin2). Green shows the busses that are used during reading and blue shows busses used during a write operation. Yellow is the address.

The provided example has 2 drawbacks:
  • It has no enable so the CE line is always asserted.
  • Reading is performed on the negative edge. This gives a worst case operation frequency of 40 MHz as Cypress specifies that the Taa3) is at most 12ns. Most of the time 50 MHz and 60 MHz will also work. For better performance (>80 MHz) you will need a pipelined design with 2 pipeline stages.
And for the record. It uses 55 LE's in a Cyclone IP1C6 (<1%).
Other SRAM modules
For projects that require some lower performance / less SRAM, I always use the IS62WV1288BLL. This is a 1Mbit (128k x 8 ), 66MHz, 1,61 SRAM ic.
To interface it we need to make the following changes to the controller.
  1. Remove BHE and BLE outputs, these are not available on the IS62WV1288BLL.
  2. Remove address line A[17] or leave it unconnected.
  3. Add a CE2 output. The IS62WV1288BLL has 2 Chip Enable inputs, one active low (CE1) and one active high (CE2). So just make CE2 the inverted output of CE by adding:

code:
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output reg CE2;
assign CE2 = !CE;



1) Price from http://nl.digikey.com
2) Also see http://www.altera.com/literature/hb/qts/qts_qii53017.pdf section: Simulating Bidirectional Pin
3) Time address to data valid
http://www.greenbird.info/img.php?h&b=sram-controller&f

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