PS/2 Keyboard Communication

By xantus on Thursday 18 February 2010 13:41 - Comments (1)
Category: Verilog examples, Views: 16.299

PS/2 keyboard communication is actually a very simply protocol too implement on a FPGA. The clock is provided by the keyboard and the data is sent in 11-bit frames. The frame-bits are:
  • 1 start bit; always 0
  • 8 data bits (LSB first)
  • 1 parity bit (odd parity)
  • 1 stop bit; always 1

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USB Communication (RS232)

By xantus on Wednesday 17 February 2010 08:01 - Comments (4)
Category: Verilog examples, Views: 5.612

The USB 2.0 capabilities are provided by the FT232RL, which is an USB to UART converter IC. So we just have to write some verilog to create an UART module to interface with the FT232RL for USB communication :) .
The verilog consists of 3 modules: baud_generator, uartrx and uarttx.

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SRAM controller

By xantus on Monday 8 February 2010 11:53 - Comments are closed
Category: Verilog examples, Views: 8.481

Sram exampleA problem with many SRAM ic's is that they are asynchronous. This is tricky too use in the synchronous FPGA world. This example shows how to interface with a cheap (€4.271)) and high speed (80 MHz) CY7C1041CV33, a 4Mbit (256k x16) SRAM ic, with a MAXII CPLD.

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4.3" PSP LCD

By xantus on Sunday 7 February 2010 15:09 - Comments are closed
Category: Verilog examples, Views: 3.022

Although the Cyclone EP1C6 does not contain enough ram bits to display graphics on this huge display. It can be used as a large character display, with the capabilities to display up to 1.620 characters (27×60) with a 8x16 font.

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By xantus on Friday 5 February 2010 20:22 - Comments are closed
Category: Verilog examples, Views: 1.737

The verilog provided at 4.3_psp_lcd can also be used to drive a VGA display. Only the timing and resolution in h_sync, v_sync and in_picture and the pixel clock in clk should be changed to the correct values as explained in vga_timing.

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