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7 Segment Displays
An easy way to add debug capabilities to your project is by using the 7-segment displays. The following piece of verilog code shows you how to control the 4 multiplexed common-cathode displays. The digitx inputs are BCD. The fifth bit (digitx[4]) is for blanking the digit (1=off, 0=on).
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VGA timing
Figure 1 illustrates the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An active-low pulse of specific duration (time a in the figure) is applied to the horizontal synchronization (hsync) input of the monitor, which signifies the end of one row of data and the start of the next. The data (RGB) input on the monitor must be driven low for a time period called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
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Rotary Encoder
The following code is for a rotary encoder with 2-bit gray code output. It has an 8-bit output which increases/decreases by rotating the rotary encoder
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PS/2 Keyboard Communication
PS/2 keyboard communication is actually a very simply protocol too implement on a FPGA. The clock is provided by the keyboard and the data is sent in 11-bit frames. The frame-bits are:
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- 1 start bit; always 0
- 8 data bits (LSB first)
- 1 parity bit (odd parity)
- 1 stop bit; always 1
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USB Communication (RS232)
The USB 2.0 capabilities are provided by the FT232RL, which is an USB to UART converter IC. So we just have to write some verilog to create an UART module to interface with the FT232RL for USB communication 
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The verilog consists of 3 modules: baud_generator, uartrx and uarttx.
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.The verilog consists of 3 modules: baud_generator, uartrx and uarttx.
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